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Freescale Semiconductor /MKV11Z7 /SIM /SOPT8

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Interpret as SOPT8

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FTM0SYNCBIT 0 (0)FTM1SYNCBIT 0 (0)FTM2SYNCBIT 0 (0)FTM3SYNCBIT 0 (0)FTM4SYNCBIT 0 (0)FTM5SYNCBIT 0 (00)CARRIER_SELECT0 0 (0)FTM0OCH0SRC 0 (0)FTM0OCH1SRC 0 (0)FTM0OCH2SRC 0 (0)FTM0OCH3SRC 0 (0)FTM0OCH4SRC 0 (0)FTM0OCH5SRC 0 (0)FTM2OCH0SRC 0 (0)FTM2OCH1SRC

FTM0OCH3SRC=0, CARRIER_SELECT0=00, FTM2SYNCBIT=0, FTM0OCH1SRC=0, FTM0OCH0SRC=0, FTM0OCH4SRC=0, FTM0OCH2SRC=0, FTM0OCH5SRC=0, FTM3SYNCBIT=0, FTM5SYNCBIT=0, FTM4SYNCBIT=0, FTM1SYNCBIT=0, FTM2OCH1SRC=0, FTM0SYNCBIT=0, FTM2OCH0SRC=0

Description

System Options Register 8

Fields

FTM0SYNCBIT

FlexTimer 0 Hardware Trigger 0 configure by software

0 (0): No effect to FTM0; this allow the hardware trigger options to function as expected. See SOPT4[FTM0TRG0SRC].

1 (1): If TRIG0 enabled, this refreshes the FTM0CNTIN and all buffered registers of the FTM0 (must write 0 first then write 1); this masks the hardware trigger.
FTM1SYNCBIT

FlexTimer 1 Hardware Trigger 0 configure by software

0 (0): No effect to FTM1; this allows the hardware trigger options to function as expected. See SOPT4[FTM1TRG0SRC].

1 (1): If TRIG0 enabled, this refreshes the FTM1CNTIN and all buffered registers of the FTM1 (must write 0 first then write 1); this masks the hardware trigger.
FTM2SYNCBIT

FlexTimer 2 Hardware Trigger 0 configure by software

0 (0): No effect to FTM2; this allows the hardware trigger options to function as expected. See SOPT4[FTM2TRG0SRC].

1 (1): If TRIG0 is enabled, this refreshes the FTM2CNTIN and all buffered registers of the FTM2 (must write 0 first then write 1); this masks the hardware trigger.
FTM3SYNCBIT

FlexTimer 3 Hardware Trigger 0 configure by software

0 (0): No effect to FTM3; this allows the hardware trigger options to function as expected. See SOPT6[FTM3TRG0SRC].

1 (1): If TRIG0 is enabled, this refreshes the FTM3CNTIN and allbuffered registers of the FTM3 (must write 0 first then write 1); this masks the hardware trigger.
FTM4SYNCBIT

FlexTimer 4 Hardware Trigger 0 configure by software

0 (0): No effect to FTM4; this allows the hardware trigger options to function as expected. See SOPT6[FTM4TRG0SRC].

1 (1): If TRIG0 is enabled, this refreshes the FTM4CNTIN and allbuffered registers of the FTM4 (must write 0 first then write 1); this masks the hardware trigger.
FTM5SYNCBIT

FlexTimer 5 Hardware Trigger 0 configure by software

0 (0): No effect on FTM5; this allows the hardware trigger options to function as expected. See SOPT6[FTM5TRG0SRC].

1 (1): If TRIG0 is enabled, this refreshes the FTM5CNTIN and allbuffered registers of the FTM5 (must write 0 first then write 1); this masks the hardware trigger.
CARRIER_SELECT0

Carrier frequency selection for FTM0/2 output channel

0 (00): FTM1_CH1 output provides the carrier signal for Timer Modulation mode

1 (01): LPTMR0 prescaler output provides the carrier signal for Timer Modulation mode

2 (10): FTM5_CH1 output provides the carrier signal for Timer Modulation mode
FTM0OCH0SRC

FTM0 channel 0 output PWM/OCMP mode source select

0 (0): FTM0CH0 pin is the output of FTM0 channel 0 PWM/OCMP

1 (1): FTM0CH0 pin is the output of FTM0 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0
FTM0OCH1SRC

FTM0 channel 1 output PWM/OCMP mode source select

0 (0): FTM0CH1 pin is the output of FTM0 channel 1 PWM/OCMP

1 (1): FTM0CH1 pin is the output of FTM0 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0
FTM0OCH2SRC

FTM0 channel 2 output PWM/OCMP mode source select

0 (0): FTM0CH2 pin is the output of FTM0 channel 2 PWM/OCMP

1 (1): FTM0CH2 pin is the output of FTM0 channel 2 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0
FTM0OCH3SRC

FTM0 channel 3 output PWM/OCMP mode source select

0 (0): FTM0CH3 pin is the output of FTM0 channel 3 PWM/OCMP

1 (1): FTM0CH3 pin is the output of FTM0 channel 3 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0
FTM0OCH4SRC

FTM0 channel 4 output PWM/OCMP mode source select

0 (0): FTM0CH4 pin is the output of FTM0 channel 4 PWM/OCMP

1 (1): FTM0CH4 pin is the output of FTM0 channel 4 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0
FTM0OCH5SRC

FTM0 channel 5 output PWM/OCMP mode source select

0 (0): FTM0CH5 pin is the output of FTM0 channel 5 PWM/OCMP

1 (1): FTM0CH5 pin is the output of FTM0 channel 5 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0
FTM2OCH0SRC

FTM2 channel 0 output PWM/OCMP mode source select

0 (0): FTM2CH0 pin is the output of FTM2 channel 0 PWM/OCMP

1 (1): FTM2CH0 pin is the output of FTM2 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0
FTM2OCH1SRC

FTM2 channel 1 output PWM/OCMP mode source select

0 (0): FTM2CH1 pin is the output of FTM2 channel 1 PWM/OCMP

1 (1): FTM2CH1 pin is the output of FTM2 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data